A typical personal computer (PC) comprises a motherboard including a microprocessor, a system bus, and a plurality of expansion slots for accommodating peripherals such as video cards, sound cards, FAX/modem cards, and the like. The system bus is coupled to both the motherboard and the slots to allow signals to be transferred between the motherboard and the cards, and between the cards themselves. Each slot is considered a "node" and the motherboard may be considered as one or more nodes depending upon the number of devices on the motherboard which are interfaced with the system bus. Because a plurality of nodes are interfaced with the system bus, an accessing scheme is needed to coordinate the transfer of signals between the nodes so that bus contention does not result.
In a typical bus accessing scheme, a node submits a bus request each time it wishes to send information signals via the system bus. This request is processed in accordance with some bus arbitration protocol and, at some time after the submission of the request, the node is granted control of the bus. Once the node has control of the bus, it sends information signals to one of the nodes coupled to the bus and waits for an acknowledgment from the receiving node. There may be certain situations, however, in which the receiving node is unable to complete the desired transaction. For example, the receiving node may have no buffers available for receiving information from the sending node. In such situations, the receiving node sends a "busy" signal to indicate that it cannot complete the transaction. Some accessing schemes at this point implement a "retry" protocol to attempt again to complete the information transfer.
The bus accessing scheme described above wastes bus bandwidth in at least two ways. First, each time information is transferred, the sending node waits for a response from the receiving node. During this waiting period, no useful information is being transferred on the bus. The bus simply sits idly by while the receiving node prepares its response. Second, where a transaction cannot be completed, all of the time spent on the system bus is wasted because no useful information was actually transferred. This leads to inefficient use of valuable bus bandwidth. In most high-end computer systems today, the system bus has already become an information bottleneck. Inefficient use of the bus only exacerbates this problem. Consequently, a need exists for a bus accessing mechanism which optimizes system bus utilization.